industrial temperature range IDT74LVC16601A 3.3v cmos 18-bit universal bus transceiver 1 january 2004 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-4599/3 features: ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ? cmos power levels (0.4 w typ. static) ? all inputs, outputs, and i/o are 5v tolerant ? supports hot insertion ? available in ssop and tssop packages functional block diagram applications: ? 5v and 3.3v mixed voltage systems ? data communication and telecommunication systems drive features: ? high output drivers: 24ma ? reduced system switching noise IDT74LVC16601A description: the lvc16601a 18-bit universal bus transceiver is built using advanced dual metal cmos technology. this 18-bit universal bus transceiver com- bines d-type latches and d-type flip-flops to allow data flow in transparent, latched and clocked modes. data flow in each direction is controlled by output-enable ( oeab and oeba ), latch-enable (leab and leba), and clock (clkab and clkba) inputs. the clock can be controlled by the clock-enable ( clkenab and clkenba ) inputs. for a-to-b data flow, the device operates in the transparent mode when leab is high. when leab is low, the a data is latched if clkab is held at a high or low logic level. if leab is low, the a-bus data is stored in the latch/ flip-flop on the low-to-high transition of clkab. output enable oeab is active low. when oeab is low, the outputs are active. when oeab is high, the outputs are in the high-impedance state. data flow for b to a is similar to that of a to b but uses oeba , leba, clkba and clkenba . all pins can be driven from either 3.3v or 5v devices. this feature allows the use of this device as a translator in a mixed 3.3v/5v supply system. the lvc16601a has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. 3.3v cmos 18-bit universal bus transceiver with 3 state outputs, 5 volt tolerant i/o clkab b 1 oeab leab leba clkenba 54 1 56 55 2 28 30 29 27 3 clkba oeba a 1 clkenab ce 1d c1 clk ce 1d c1 clk to 17 other channels
industrial temperature range 2 IDT74LVC16601A 3.3v cmos 18-bit universal bus transceiver ssop/ tssop top view pin configuration symbol description max unit v term terminal voltage with respect to gnd ?0.5 to +6.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, ?50 ma i ok v i < 0 or v o < 0 i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 6.5 8 pf c i/o i/o port capacitance v in = 0v 6.5 8 pf capacitance (t a = +25c, f = 1.0mhz) oeab a 1 gnd a 2 a 3 v cc a 4 a 5 gnd a 6 a 7 a 8 a 9 a 11 a 12 gnd a 13 a 14 a 15 v cc a 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 49 50 51 52 53 54 55 56 1 clkenab b 1 gnd b 2 b 3 v cc b 4 b 5 b 6 b 7 b 8 b 9 gnd b 11 b 12 b 13 b 14 gnd b 15 b 16 b 17 gnd a 18 oeba leba 25 26 27 28 32 31 30 29 gnd b 18 clkba clkenba a 10 a 17 v cc b 10 leab clkab notes: 1. h = high voltage level x = don?t care l = low voltage level z = high-impedance = low-to-high transition 2. a-to-b data flow is shown. b-to-a data flow is similar but uses oeba , leba, clkba, and clkenba . 3. output level before the indicated steady-state input conditions were established. 4. output level before the indicated steady-state input conditions were established, provided that clkab was high before leab went low. inputs outputs clkenab oeab leab clkab ax bx xhxxxz xlhxll xlhxhh hllxxb (3) lll ll lll hh l lllxb (3) lllhxb (4) function table (1,2) pin names description oeab a-to-b output enable input (active low) oeba b-to-a output enable input (active low) leab a-to-b latch enable input leba b-to-a latch enable input clkab a-to-b clock input clkba b-to-a clock input a x a-to-b data inputs or b-to-a 3-state outputs b x b-to-a data inputs or a-to-b 3-state outputs clkenab a-to-b clock enable input (active low) clkenba b-to-a clock enable input (active low) pin description
industrial temperature range IDT74LVC16601A 3.3v cmos 18-bit universal bus transceiver 3 symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input leakage current v cc = 3.6v v i = 0 to 5.5v ? ? 5a i il i ozh high impedance output current v cc = 3.6v v o = 0 to 5.5v ? ? 10 a i ozl (3-state output pins) i off input/output power off leakage v cc = 0v, v in or v o 5.5v ? ? 50 a v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v v in = gnd or v cc ?? 10a i cch i ccz 3.6 v in 5.5v (2) ?? 10 ? i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 500 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c notes: 1. typical values are at v cc = 3.3v, +25c ambient. 2. this applies in the disabled state only. note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 6ma 2 ? v cc = 2.3v i oh = ? 12ma 1.7 ? v cc = 2.7v 2.2 ? v cc = 3v 2.4 ? v cc = 3v i oh = ? 24ma 2.2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 6ma ? 0.4 i ol = 12ma ? 0.7 v cc = 2.7v i ol = 12ma ? 0.4 v cc = 3v i ol = 24ma ? 0.55
industrial temperature range 4 IDT74LVC16601A 3.3v cmos 18-bit universal bus transceiver operating characteristics, v cc = 3.3v 0.3v, t a = 25c symbol parameter test conditions typical unit c pd power dissipation capacitance per transceiver outputs enabled c l = 0pf, f = 10mhz pf c pd power dissipation capacitance per transceiver outputs disabled switching characteristics (1) v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. unit t plh propagation delay ? 5.4 ? 4.6 ns t phl ax to bx or bx to ax t plh propagation delay ? 6.2 ? 5.2 ns t phl leba to ax, leab to bx t plh propagation delay ? 6.3 ? 5.3 ns t phl clkba to ax, clkab to bx t pzh output enable time ? 6.8 ? 5.6 ns t pzl oeba to ax, oeab to bx t phz output disable time ? 6 ? 5.2 ns t plz oeba to ax, oeab to bx t su set-up time high or low, ax to clkab, bx to clkba 1.5 ? 1.5 ? ns t h hold time high or low, ax to clkab, bx to clkba 0.8 ? 0.8 ? ns t su set-up time high or low clock low 1 ? 1 ? ns ax to leab, bx to leba clock high 1 ? 1 ? t su set-up time, clkenab to clkab 2.1 ? 2.1 ? ns t su set-up time, clkenba to clkba 2.1 ? 2.1 ? ns t h hold time high or low, ax after leab, bx after leba 1.8 ? 1.8 ? ns t h hold time, clkenab after clkab 0.5 ? 0.5 ? ns t h hold time, clkenba after clkba 0.5 ? 0.5 ? ns t w leab or leba pulse width high 3 ? 3 ? ns t w clkab or clkba pulse width high or low 3 ? 3 ? ns t sk (o) output skew (2) ?? ? 500 ps notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction.
industrial temperature range IDT74LVC16601A 3.3v cmos 18-bit universal bus transceiver 5 open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1, 2) lvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 lvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t lvc link data input 0v 0v 0v 0v t rem timing input asynchronous control synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t lvc link low-high-low pulse high-low-high pulse v t t w v t lvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v ol+ v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v oh- v hz lvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 10mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 10mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range 6 IDT74LVC16601A 3.3v cmos 18-bit universal bus transceiver ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xx lvc xxxx xx package device type temp. range pv pa 16 74 shrink small outline package thin shrink small outline package 18-bit universal bus transceiver -40c to +85c xxx family bus-hold 601a no bus-hold double-density, 24ma blank
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